1. Field of the Invention
The invention relates to digital field effect transistor amplifier circuits which provide an output signal level substantially equal to the power supply voltage for use in connecting one or more field effect transistor gating circuits to a large plurality of other field effect transistor gating circuits or for connecting field effect transistor gating circuits to a long circuit network having a large distributed signal conductor to reference conductor capacitance.
2. Description of the Prior Art
FIG. 1 shows a simple inverter circuit embodied in field effect transistors having a load FET 11 connected to operate as a load resistor for providing a binary up level voltage and a switching FET 13 which is operated in the triode region when a positive voltage signal A is present at its gate to provide a binary zero level voltage by having a conductivity substantially greater than the conductivity of FET 11. The greater conductivity is provided by making the channel region of FET 13 five times as wide as it is long. If FET 11 and FET 13 were P-type field effect transistors, operable with a negative gate voltage signal, and connected to a negative power supply, a binary up level voltage would be negative. Because FET 11 is nonlinear, only negligible currents will flow through FET 11 until a gate to source threshold voltage Vth is exceeded. The output signal A therefore swings from nearly ground reference voltage to an upper binary voltage of +8 volts minus Vth where Vth is the threshold voltage. Vth is fully defined in "MOSFET in Circuit Design" by Robert H. Crawford, Copyright 1967, by Texas Instruments, Inc.
In order to provide an output voltage equal to +8 volts, FET 11 must be provided with a gate voltage substantially higher than +8 volts. The higher gate voltage has been provided in the prior art by a separate power supply or by a self-charging bootstrap capacitor circuit such as shown in FIG. 2.
One problem with the ordinary self-charging bootstrap capacitor circuit such as is shown in FIG. 2 is that node 29 of FIG. 2 has no discharge path other than ordinary leakage current paths and, therefore, whenever FET 23 is turned on, it must draw current from FET 21 as well as the output circuit net capacitance discharging current. Furthermore, the resistivity of FET 21 is much lower than was the resistivity of FET 11 of FIG. 1 because FET 21 has a much higher gate voltage. The current Id through an FET is proportional to (Vg-Vth).sup.2 where Vg is the gate voltage. The increased current allows the output voltage at NODE 31 to rise much faster. Because FET 23 must carry both of these currents, the voltage at the output node 31 will drop slowly when FET 23 is turned on unless a relatively large FET 23 is provided. In the example of FIG. 2, bootstrap load devices 21 and 25 are shown having a width to length ratio of one to one. In other words, the width of the channel regions of these field effect transistors is approximately equal to the length of the channel regions. On the other hand, the width of the channel regions of FET 23 is only five times the length of its channel region to provide the normally lower resistivity when a signal voltage A is present at its gate input. To decrease output signal fall time, a ratio of greater than five to one will be required.
If a discharge device is provided to discharge the bootstrapped node such as FET 33 connected between ground reference potential and node 29, both sides of the bootstrap capacitor 27 can be simultaneously discharged allowing a faster output signal fall time without increasing the width to length ratio of the switching transistor FET 23. The use of a discharge FET 33 in conjunction with the ordinary bootstrap capacitor bias circuit as shown in FIG. 2 will not work in those applications where it is desired to selectively render switching device 23 conductive unless discharge device 33 is simultaneously rendered conductive and, furthermore, is not rendered conductive at any other times. If discharge FET 33 is rendered conductive to discharge node 29, the output net capacitance of node 31 will be also partially discharged by the voltage divider effect between the output net capacitance and the bootstrap capacitor 27. This partial discharge will result in the voltage at output node 31 being reduced to a level of less than a minimum binary up level voltage even though switching FET 23 was not rendered conductive by an input signal A.
Another difficulty with the use of an ordinary self-charging bootstrap capacitor circuit, such as shown in FIG. 2, it that two of such circuits cannot be connected in series to provide a higher gate voltage to a switching FET than one bootstrap capacitor bias circuit alone would be able to provide. Higher gate voltages are desirable to allow a relatively narrow field effect transistor to conduct more current. Referring to FIG. 3, two such ordinary self-charging bootstrap capacitor circuits have been connected in series. The circuit of FIG. 3 also uses clock phase signal to gate the FET devices as taught in U.S. Pat. Nos. 3,601,627 and 3,638,036 to reduce power dissipation. FET 45 and FET 43 provide a current path in series to charge bootstrap capacitor node 49 to +8 volts minus Vth. After bootstrap capacitor 47 has been charged, the clock pulse signal labeled .phi.1 returns to a ground reference voltage turning FET 43 and FET 45 off. In theory, when FET 43 turns off, node 51 is allowed to rise providing a series current path through FET 41 and FET 59 to charge capacitor 57 to a voltage substantially equal to +8 volts. When FET 59 is rendered nonconducting, however, the output node 61 does not rise to 8 volts but remains a full threshold Vth below 8 volts because node 51 is clamped to 8 volts by FET 41 which still has a large positive voltage at its gate input node 49.
If the input to discharging FET 53 is connected to an input signal such as clock phase three, node 49 will be discharged at the same time as node 61 is allowed to rise, thereby turning off device 41. However, because of the voltage divider effect of capacitors 47 and 57, node 51 will be partially discharged and again a reduced output voltage will be generated.